library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.processor_types.all;

entity program_counter is
	port (
		clock: in std_ulogic;
        reset: in std_ulogic;
		jump_select: in std_ulogic;
        branch_select : in std_ulogic;
		jump_value: in bit32;
		null_flag: in std_ulogic;
        incr_pc : in std_ulogic;
		pc_value: out bit32
	);
end program_counter;

architecture arch_pc of program_counter is
	signal pc: natural;
begin
	-- psl property psl_pc is
	--   never (branch_select and jump_select);
	-- psl assert psl_pc;
	
	seq: process(clock, reset)
	begin
        if (reset='1') then
            pc <= 0;
        elsif (rising_edge(clock)) then
            if (incr_pc = '1') then
				pc <= pc + 4;
            elsif ((branch_select = '1' and null_flag = '1') or jump_select='1') then
                pc <= to_integer(unsigned(jump_value));
			end if;
		end if;
	end process;
	pc_value <= std_logic_vector(to_unsigned(pc, 32));
end arch_pc;
